In standard cell layout synthesis, routing is performed in several stages. In one stage, contact pin locations for source and drain connections of transistors are identified and contacts are generated to allow metal interconnections to electrically connect to the source/drain areas.
Supply nets, which connect the transistors to power and ground, are generally routed in specific routing layers prior to the routing of signal nets. During subsequent stages of routing, an area router is used to complete connecting signal nets and any remaining supply nets, typically using polysilicon and metal-1 interconnection layers. The placement of source/drain contact pins has a significant impact upon the quality of final routing of a standard cell design.
For example, referring to prior art FIG. 1, assume the net labeled NET-1 105 was the first net selected to be routed following the placement of all of the contact pins within the standard cell portion 100, and routed as indicated in FIG. 1 using a metal-1 interconnection layer. Subsequently, NET-2 107 was routed producing the layout indicated in FIG. 1. As a result of the contact pin labeled 110 residing directly between the contact pins labeled 120 and 121, the NET-1 105 cannot connect the contact pins 120 and 121 to each other with a straight interconnection for NET-1 105. As a result, the router uses vertical interconnection to avoid, or jog around, the contact 110 and routes interconnection into the area between the PMOS diffusion 102 and the NMOS diffusion 104 in order to complete the net connection. Next, NET-2 107 is routed.
The routing of NET-2 107 required the interconnection to go around NET-1 105. When contrasted to prior art FIG. 2 which illustrates the same example where the NET-2 was the first net to be routed, it can be seen that the length of the routed NET-2 207 is much less than the length of the routed NET-2 107 of FIG. 1, while producing a NET-1 205 having a length equal to that of NET-1 105 of FIG. 1.
One prior art method of overcoming the dependency on routing order is for a user to specifically indicate that the NET-2 needs to be routed before the NET-1. However, this is often not possible in that a user often does not have visibility to the relationships between the nets prior to the routing steps, and there could be a large number of nets making it difficult to prioritize nets optimally. Subsequent analysis of the attempted routing would allow for a user to define specific net routing priorities such that a second pass at routing could perform a better result. However, this manual intervention is inefficient use of time and often results in significant time delays.
The use of post-processing reroute is another technique used to optimize the layout of semiconductor circuits. Post-processing reroute occurs following an attempt to route all nets within a design circuit. During post-processing reroute, nets are individually analyzed to determine whether or not they can be routed in a more efficient manner. For example, for the circuit of FIG. 1, a post-processing reroute would determine that NET-2 107 can be more efficiently rerouted by first removing the routed NET-1 105 and then rerouting the NET-2 107. Following the rerouting of the NET-2 the NET-1 would then in turn be rerouted and the better result of FIG. 2 can be obtained.
However, the use of post-processing reroute is a time and resource consuming process which does not improve router access to the contact pins. Referring to the prior art FIG. 1, the pins 120, 110, and 121 are arranged as such that the router access to pin 110 is available only from top and bottom directions and not from the left and right. Even in the optimal routing as illustrated in FIG. 2, the router in the routing of NET-1 had to go around the contact pin 210 in order to make a connection between the pins 220 and 221. The need to route around other contact pins illustrates limited router access which is a function of contact pin placement.
Another known contact placement technique is to specify contact to a predefined location for each source/drain area. For example, the contact pin location where routing is to occur can be predefined to be at the center or the top or bottom edge of a drain/source area. Standard cell synthesis tools using channel routing have used the contact pin placement in the center of the source/drain region and metal interconnections from contact pins to the channel edge, allowing subsequent channel routing. As a result of this generic placement of contact pins, router access to these pins is often diminished.
Therefore, the ability to automatically optimize a placement of source/drain contact pins in order to improve router access, reduce routing dependency upon net ordering and minimize the number of routing tracks used by a router would be beneficial.